Title :
Direct digital frequency synthesizer architecture based on Chebyshev approximation
Author :
Palomäki, Kalle I. ; Niittylahti, Jarkko
Author_Institution :
Digital & Comput. Syst. Lab., Tampere Univ. of Technol., Finland
fDate :
Oct. 29 2000-Nov. 1 2000
Abstract :
This paper presents a Chebyshev approximation based method for digital quadrature sine and cosine waveform synthesis. The spurious performance of the Chebyshev approximation is improved by applying the symmetry properties between sine and cosine signals. The frequency synthesizer is modelled with register transfer level VHDL. Simulation and synthesis results of the Chebyshev sinusoidal signal synthesizer are presented and compared with other direct digital sine and cosine synthesizers. The synthesis is carried out on a 0.35 /spl mu/m, 3.3 V, 4-metal, n-well standard cell process. According to the synthesis results the total design area is 5900 gates and the maximum system clock frequency 160 MHz.
Keywords :
CMOS logic circuits; Chebyshev approximation; direct digital synthesis; phase convertors; pipeline processing; 0.35 micron; 160 MHz; 3.3 V; 4-metal n-well standard cell process; Chebyshev approximation; Chebyshev sinusoidal signal synthesizer; cosine waveform synthesis; direct digital frequency synthesizer architecture; performance; register transfer level VHDL; sine waveform synthesis; symmetry properties; total design area; Chebyshev approximation; Clocks; Computer architecture; Equations; Frequency control; Frequency synthesizers; Laboratories; Read only memory; Registers; Signal synthesis;
Conference_Titel :
Signals, Systems and Computers, 2000. Conference Record of the Thirty-Fourth Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-6514-3
DOI :
10.1109/ACSSC.2000.911267
