Author :
Aimadeddine, M. ; Jousseaume, V. ; Amal, V. ; Favennec, L. ; Farcy, A. ; Zenasni, A. ; Assous, M. ; Vilmay, M. ; Jullian, S. ; Maury, P. ; Delaye, V. ; Jourdan, N. ; Vanypre, T. ; Brun, P. ; Imbert, G. ; Lefriec, Y. ; Mellier, M. ; Chaabouni, H. ; Chapelo
Abstract :
An Ultra Low-K (ULK) SiOCH porous dielectric with k=2.3 targeted for the 32 nm node is integrated at local and intermediate levels with the Trench First Hard Mask architecture currently implemented for the 65/45 nm nodes. Physical and electrical characterizations after integration show good barrier integrity, substantial gain in capacitance as well as good via chain functionality. The material exhibits similar interline leakage and breakdown field than the k=2.5 reference dielectric meeting specifications of the 32 nm node.
Keywords :
CMOS integrated circuits; dielectric thin films; electric breakdown; integrated circuit interconnections; leakage currents; masks; organic compounds; porous materials; CMOS technology; Trench First Hard Mask architecture; ULK SiOCH porous dielectrics integration; breakdown field; electrical characterizations; high performance BEOL; interconnect induced RC delay; interline leakage; size 32 nm; CMOS technology; Chemicals; Delay; Dielectric constant; Dielectric materials; Plasma chemistry; Plasma materials processing; Plasma properties; Robustness; Skeleton;
