A Low-Latency and High-Power-Efficient On-Chip LVDS Transmission Line Interconnect for an RC Interconnect Alternative

Author

Ito, Hiroyuki ; Seita, Junki ; Ishii, Takahiro ; Sugita, Hideyuki ; Okada, Kenichi ; Masu, Kazuya

Author_Institution

Integrated Res. Inst., Yokohama

fYear

2007

fDate

4-6 June 2007

Firstpage

193

Lastpage

195

Abstract

This paper demonstrates a low voltage differential signaling (LVDS)-type on-chip transmission line (TL) interconnect to solve delay issues on a global interconnect. The proposed TL interconnect can achieve 10 Gbps signaling with 2.7 mW power consumption. The on-chip LVDS TL interconnect has the best power efficiency for on-chip interconnects at over 1 mm. Delay variation of the TL interconnect is 89 % smaller than that of the conventional RC interconnect.

Keywords

RC circuits; delay circuits; integrated circuit interconnections; low-power electronics; transmission line theory; RC interconnect; bit rate 10 Gbit/s; low voltage differential signaling; on-chip LVDS; on-chip interconnects; on-chip transmission line interconnect; power 2.7 mW; power efficiency; CMOS technology; Crosstalk; Delay; Energy consumption; Integrated circuit interconnections; Large scale integration; Low voltage; Power transmission lines; Timing; Transmission lines;

fLanguage

English

Publisher

ieee

Conference_Titel

International Interconnect Technology Conference, IEEE 2007

Conference_Location

Burlingame, CA

Print_ISBN

1-4244-1069-X

Electronic_ISBN

1-4244-1070-3

Type

conf

DOI

10.1109/IITC.2007.382387

Filename

4263699