Electrical characterization of through-wafer interconnects

Author

Lawrence, T.E. ; Donovan, S.M. ; Knowlton, W.B. ; Rush-Byers, J. ; Moll, A.J.

Author_Institution

Electr. & Comput. Eng. Dept., Boise State Univ., USA

fYear

2004

fDate

2004

Firstpage

99

Lastpage

102

Abstract

Through-wafer interconnects (TWI) allows 3-D chip stacking enabling integration of multiple chip functions (i.e. opto-electronic, analog or digital) with reduced power and space requirements. To date, non-destructive characterization techniques for determining interconnect integrity and reliability have not been developed. This work examines a specially modified electrical four-point probe for non-destructive characterization of TWI´s. Technical challenges and measurement optimization methods are reported.

Keywords

design of experiments; electric resistance measurement; integrated circuit interconnections; integrated circuit measurement; integrated circuit reliability; 3-D chip stacking; copper plating anomalies; design of experiment; electrical characterization; interconnect integrity; interconnect reliability; modified four-point probe; multiple chip functions integration; nondestructive characterization; numerical model; reduced power requirements; reduced space requirements; sensitive resistance measurement; through-wafer interconnects; Cables; Copper; Electric variables measurement; Electrical resistance measurement; Force measurement; Integrated circuit interconnections; Optical sensors; Power system interconnection; Probes; Stacking;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electron Devices, 2004 IEEE Workshop on

Print_ISBN

0-7803-8369-9

Type

conf

DOI

10.1109/WMED.2004.1297363

Filename

1297363