Title :
Non-linear DAC implementations in DDFS
Author :
Zhou, Zhihe ; Horowitz, Irwin ; La Rue, George S.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
Abstract :
A technique to reduce ROM size and therefore power dissipation in direct digital frequency synthesizers (DDFS) is to use a non-linear DAC to approximate the sine function. Piecewise-linear and piecewise-quadratic approximations were investigated for a 12, 14 and 16-bit non-linear DAC in terms of the required ROM size, achievable spurious-free dynamic range (SFDR) and implementation complexity. Results show that 94 dB SFDR can be achieved using a 16-segment quadratic approximation, DAC resolution of 14-bits and a 5-bit squaring circuit. The required ROM size is only 256 bits.
Keywords :
digital-analogue conversion; direct digital synthesis; nonlinear network synthesis; piecewise linear techniques; piecewise polynomial techniques; read-only storage; waveform generators; 256 bit; DAC resolution; DDFS; ROM size reduction; SFDR; direct digital frequency synthesizers; nonlinear DAC implementation; piecewise-linear approximation; piecewise-quadratic approximation; sine function approximation; spurious-free dynamic range; squaring circuit; Circuits; Computer science; Dynamic range; Frequency synthesizers; Piecewise linear techniques; Power dissipation; Programmable logic arrays; Read only memory; Spread spectrum communication; Switches;
Conference_Titel :
Microelectronics and Electron Devices, 2004 IEEE Workshop on
Print_ISBN :
0-7803-8369-9
DOI :
10.1109/WMED.2004.1297372
