Title :
A 3 mu m pitch multilevel interconnect system for VLSI devices
Author :
Monk, J.L. ; Keith, A.C. ; Albano, R.A. ; Samuels, B.C. ; Riley, P.E. ; Blaha, F.C. ; Cricchi, J.R.
Author_Institution :
Westinghouse Electr. Corp., Baltimore, MD, USA
Abstract :
A multilevel interconnection system having 1- mu m features with a 3- mu m pitch, including contact pads for use in CMOS VLSI devices, is presented. Reflowed borophosphosilicate glass is used as the first layer dielectric for partial planarization. A highly selective two-step etch process is used to form the 1.2- mu m contacts. The interconnect system has proven to be successful in fabrication of 1.25- mu m CMOS VLSI gate arrays and memories on both bulk silicon and silicon-on-sapphire materials.<>
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; metallisation; 1.25 micron; 3 micron; B/sub 2/O/sub 3/P/sub 2/O/sub 5/SiO/sub 2/; CMOS VLSI; SOS; Si-Al/sub 2/O/sub 3/; contact pads; feature size; first layer dielectric; gate arrays; memories; multilevel interconnect system; partial planarization; pitch; reflowed borophosphosilicate glass; selective two-step etch process; Annealing; Cleaning; Dielectrics; Etching; Glass; Inductors; Monitoring; Plasma applications; Silicon; Very large scale integration;
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1988. Proceedings., Fifth International IEEE
Conference_Location :
Santa Clara, CA, USA
DOI :
10.1109/VMIC.1988.14176
