• DocumentCode
    29658
  • Title

    Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics

  • Author

    Yen-Lung Chen ; Wan-Rong Wu ; Liu, C.-N.J. ; Li, James Chien-Mo

  • Author_Institution
    Nat. Central Univ., Jungli, Taiwan
  • Volume
    33
  • Issue
    1
  • fYear
    2014
  • fDate
    Jan. 2014
  • Firstpage
    24
  • Lastpage
    35
  • Abstract
    Flexible electronics are a possible alternative for portable consumer applications and have many advantages. However, the circuit design for flexible electronics is still challenging, especially for sensitive analog circuits. Due to the different properties of flexible thin-film transistors (TFTs), conventional CMOS design techniques cannot be used directly on flexible electronics. Significant parameter variations and degradation effects of flexible TFTs further increase difficulties for circuit designers. In this paper, a reliability-aware circuit sizing approach is proposed for the analog circuits with flexible TFTs. The process variation, bending, and degradation effects of flexible TFTs in the optimization flow are considered simultaneously. Instead of optimizing the fresh yield and lifetime yield separately, a unified optimization approach is proposed to consider the two yield issues simultaneously. As shown in the experimental results, the proposed approach can further improve the lifetime yield and significantly reduce the design overhead with a fast computation time.
  • Keywords
    analogue circuits; computational complexity; flexible electronics; integrated circuit design; optimisation; thin film transistors; TFT; bending effects; circuit design; degradation effects; design overhead reduction; fast computation time; flexible electronics; flexible thin-film transistors; fresh yield; lifetime yield; parameter variations; portable consumer applications; reliability-aware circuit sizing approach; sensitive analog circuits; unified optimization approach; Analog circuits; CMOS integrated circuits; Degradation; Mathematical model; Optimization; Thin film transistors; Degradation; parametric yield; performance optimization; transistor sizing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2013.2282757
  • Filename
    6685879