Very short locking time PLL based on controlled gain technique

In this paper, we describe a novel PLL circuit design with a variable control gain technique. The proposed PLL includes a Phase-Frequency Detector (PFD), a Variable Controlled Gain Charge Pump (VCGCP) based on a frequency detector and a Frequency-to-Voltage Converter (FVC), a Differential Voltage Controlled Oscillator (DVCO) and a frequency divider. First, the PLL reacts quickly and accelerates convergence using the high gain charge pump, then when the frequency deviation decreases, then the VCGCP changes the gain in the same drift. It also ensures a better stability, a shorter locking time, and as a result, a low jitter is obtained. Two PLL circuits were simulated under the same conditions: the first one uses VCGCP technique and locks after 560 ns, while the second classical PLL locks after 5 μs