Multichip packaging technology with laser-patterned interconnects

A multichip silicon-on-silicon packaging technology that incorporates laser-patterned thin-film interconnects is described. This technology is particularly suited for application in high-speed, high-power, high-I/O systems where it provides many advantages over more traditional methods. The laser-patterned thin-film interconnects allow higher I/O densities and better electrical performance than wire bonds or tape automated bonding (TAB). The face-up, thin-film eutectic die-attach technique used provides much lower thermal resistance between the substrate and the chips than solder bump die attach can achieve. In addition, laser-patterned interconnects demonstrate superior ruggedness and fatigue resistance under thermomechanical cycling and shock. This technology has been used to produce a 10-chip memory module, samples of which have been tested using relevant methods of MIL-STD 883C