Comparing defect coverage for current-mode logic and CMOS VLSI cells

Author

Rozon, Come ; Al-Khalili, Dhamin ; Adham, Saman ; Racz, Douglas

Author_Institution

R. Mil. Coll. of Canada, Kingston, Ont., Canada

Volume

1

fYear

2000

fDate

2000

Firstpage

429

Abstract

This paper presents a comprehensive defect analysis of a 0.8 μm BiCMOS fabrication technology. The study involved both current-mode logic (CML) and complementary metal oxide semiconductor (CMOS) devices, The analysis is based on defect macro models which are used to perform a comprehensive study for each bipolar and each MOS transistor where both hard and soft defects are present. This detailed study shows that although fault coverage can reach 100% by combining different methods of testing, the defect coverage does not reach this level for logic components

Keywords

BiCMOS logic circuits; VLSI; current-mode logic; fault diagnosis; integrated circuit modelling; 0.8 micron; BiCMOS fabrication technology; CMOS VLSI cells; current-mode logic; defect coverage; defect macro models; fault coverage; hard defects; soft defects; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Fabrication; Logic devices; Logic testing; MOSFETs; Performance analysis; Semiconductor device modeling; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on

Conference_Location

Jounieh

Print_ISBN

0-7803-6542-9

Type

conf

DOI

10.1109/ICECS.2000.911572

Filename

911572