Power minimization in heterogeneous processing

Optimizing power during the partitioning and scheduling of tasks on to multiple heterogeneous VLSI processors is an important new problem. This paper presents a new methodology and initial analysis of power in heterogeneous systems for real-time computationally-intensive applications. Minimization of latency and interprocessor communication are studied along with voltage scaling techniques to study relative power savings. Task duplication, data regeneration, loop winding and loop unrolling are also supported. A large, complex, real industrial application-audio compression, donated by Motorola-is used to study the power savings using different heterogeneous system implementations. Results show that up to 10-fold improvement in estimated power is attainable for this complex application. Data regeneration, task duplication and loop unrolling techniques provided up to 51%, 6% and 20% savings in power respectively. This research is important for industry, since power dissipation considerations at the early stages of design are crucial for mapping high-performance applications into cost-efficient and reliable heterogeneous systems