Title :
Area time power estimation for FPGA based designs at a behavioral level
Author :
Bilavarn, S. ; Gogniat, Guy ; Ippe, Jea N Luc Phil
Author_Institution :
Centre de Recherche, LESTER, Lorient, France
Abstract :
A new performance estimation technique for FPGA implementation based designs is presented. The interest and originality of the method is to rapidly test a great number of implementation solutions while staying independent as far as possible of the technology used, and to include power consumption estimation. Thanks to this method, the designer can quickly have realistic information about the performances of a design, starting from a behavioral specification
Keywords :
field programmable gate arrays; formal specification; high level synthesis; resource allocation; FPGA based designs; area time power estimation; behavioral level; behavioral specification; performance estimation technique; power consumption estimation; Array signal processing; Bismuth; Design methodology; Field programmable gate arrays; High level synthesis; Process design; Signal processing algorithms; Space technology; Testing; Time factors;
Conference_Titel :
Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on
Conference_Location :
Jounieh
Print_ISBN :
0-7803-6542-9
DOI :
10.1109/ICECS.2000.911593
