Title :
A multiphase partitioner and scheduler for distributed memory systems
Author :
Pande, Santosh ; Bali, Tareq
Author_Institution :
School of Electr. Eng. & Comput. Sci., Ohio Univ., Athens, OH, USA
Abstract :
Most of the current loop partitioning methods for distributed memory systems first partition program data (either automatically or through user specified distributions) and then use `owner computes´ rule to to localize the underlying references. Since parallelism is an inherent characteristic of the code, for aggressive optimizations, one should take an orthogonal approach of first partitioning the code to maximize the parallelism and then allocate data appropriately. We describe a multiphase partitioner and scheduler based on the above motivation which consists of five phases. First, the code partitioning phase determines a set of directions for minimizing the communication by trading the parallelism to a certain extent. Next, the data distribution phase attempts to achieve computation+communication load balance by distributing the underlying data. The granularity adjustment phase attempts to further eliminate communication to minimize completion time. Finally, the load balancing phase attempts to reduce the number of processors without degrading the completion time and the mapping phase schedules the partitions on available processors
Keywords :
distributed memory systems; optimisation; parallel programming; processor scheduling; resource allocation; aggressive optimizations; code partitioning; communication load balance; computation load balance; data allocation; data distribution phase; distributed memory systems; granularity adjustment phase; loop partitioning methods; mapping phase; minimized communication; minimized completion time; multiphase partitioner; multiphase scheduler; orthogonal approach; parallelism; processors; scheduling; Computer science; Concurrent computing; Delay; Distributed computing; Distributed power generation; Electronic mail; Load management; Parallel processing; Partitioning algorithms; Processor scheduling;
Conference_Titel :
System Sciences, 1996., Proceedings of the Twenty-Ninth Hawaii International Conference on ,
Conference_Location :
Wailea, HI
Print_ISBN :
0-8186-7324-9
DOI :
10.1109/HICSS.1996.495505