A novel round function architecture for AES encryption/decryption utilizing look-up table

Author

Wang, Jhing-Fa ; Chang, Sun-Wei ; Lin, Po-Chuan

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

2003

fDate

14-16 Oct. 2003

Firstpage

132

Lastpage

136

Abstract

We present an intellectual property (IP) core of the entire advanced encryption standard (AES) algorithm. Our design utilizes the T-box algorithm to implement the Rijndael round function. By analyzing the pipelining dataflow, a new architecture, which combines the multiplexing and the iteration architecture, is also proposed. The designs are implemented using the integrated systems engineering (ISE) 5.1i software on a single Virtex-E XCV812E field programmable gate array (FPGA) device. As a result, the AES IP core operates at 61MHz with the key scheduler resulting in a throughput of l.9Gbps for the AES encryption and decryption with the block size of 128 bits and the flexible key size. A comparison is provided between our design and similar existing implementations.

Keywords

cryptography; system-on-chip; table lookup; FPGA; Rijndael round function; T-box algorithm; advanced encryption standard algorithm; decryption; integrated systems engineering; intellectual property; iteration architecture; pipelining dataflow; security chip; single Virtex-E XCV812E field programmable gate array device; Algorithm design and analysis; Computer architecture; Cryptography; Data analysis; Design engineering; Field programmable gate arrays; Intellectual property; Pipeline processing; Systems engineering and theory; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Security Technology, 2003. Proceedings. IEEE 37th Annual 2003 International Carnahan Conference on

Print_ISBN

0-7803-7882-2

Type

conf

DOI

10.1109/CCST.2003.1297549

Filename

1297549