A submicron CMOS two level metal process with planarization techniques

A double-level meal submicron CMOS process is presented that uses planarization techniques for all possible layers. The authors describe the planarization of poly gates by resist etch back (REB), contact-hole filling with CVD tungsten, intermetal dielectric planarization with a sacrificial layer, and via filling with CVD tungsten. The topography of this CMOS process is given by a field oxide (350 nm), one poly layer (500 nm), and two metal layers (metal 1: 900 nm; metal 2: 1100 nm). Electrical results are given.<>