Ray tracing on an architecture built from reusable IP components

When designing a massively multi-core processor, evaluating the addition of a per core feature such as a SIMD unit, multithreading, or a large cache needs to take account of the following question: ldquoIf I didnpsilat have that feature per core, how many extra simple cores could I add with the area saved?rdquo Irregular algorithms such as ray tracing are widely expected to drive graphics architectures toward a more general programming model, the details of which are still open to investigation. We are prototyping an architecture based on general-purpose embedded cores through cycle-accurate modelling following an ESL design approach. We expect in our initial results to cast light on the trade-offs between different uses of a fixed budget of silicon area when given the choice to add features to a core, to add cache capacity, or to add more cores of a simple nature when ray tracing is used as the benchmark.