DocumentCode
2968112
Title
An FPGA implementation of whitted-style ray tracing accelerator
Author
Park, Woo-Chan ; Nah, Jae-ho ; Park, Jeong-Soo ; Lee, Kyung-Ho ; Kim, Dong-Seok ; Kim, Sang-Duk ; Park, Jin-Hong ; Kim, Cheong-Ghil ; Kang, Yoon-Sig ; Yang, Sung-Bong ; Han, Tack-Don
Author_Institution
Dept. of Comput. Eng., Sejong Univ., Seoul
fYear
2008
fDate
9-10 Aug. 2008
Firstpage
187
Lastpage
187
Abstract
This paper presents an FPGA implementation of a full whitted-style ray tracing accelerator. It achieves about 1.3 M rays per second over realistic 3 D scenes. The future implementation with ASIC is expected to achieve real-time performance.
Keywords
computer graphic equipment; field programmable gate arrays; FPGA implementation; Whitted-style ray tracing accelerator; field programmable gate arrays; graphics processors; Acceleration; Application specific integrated circuits; Computer science; Field programmable gate arrays; Layout; Pipelines; Prototypes; Random access memory; Ray tracing; Robot kinematics; FPGA implementation; I.3.1 [Hardware Architecture]: Graphics processors; Ray tracing;
fLanguage
English
Publisher
ieee
Conference_Titel
Interactive Ray Tracing, 2008. RT 2008. IEEE Symposium on
Conference_Location
Los Angeles, CA
Print_ISBN
978-1-4244-2741-3
Type
conf
DOI
10.1109/RT.2008.4634650
Filename
4634650
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