Improvement of CMOS-MEMS accelerometer using the symmetric layers stacking design

This study presents a novel CMOS-MEMS capacitive type accelerometer design which consists of symmetric layers (4 metal and 3 dielectric layers) stacking to reduce the bending of suspended structures due to thin film residual stresses. Thus, the capacitance loss caused by the mismatch of sensing electrodes is reduced. Moreover, structures with symmetric layers stacking have less thermal deformation by temperature variation. A simple post-CMOS process including oxide wet-etching and dry XeF₂ etching is established to fabricate the device. Measurement shows maximum bending deformation of a suspended 390μm×430μm structure is only 1μm, and mismatch of fixed and movable sensing electrodes is reduced to 1μm. The bending curvature has only ~2% change as temperature increased 80°C. The sensitivity of this accelerometer is 1.46mV/G (in comparison, the accelerometer with asymmetric layers stacking structure has sensitivity of 0.07mV/G), and the noise level is 0.35mG/√Hz.