A low power memory cell design for SEU protection against radiation effects

This paper presents a novel soft error tolerant SRAM cell design based on the concept of partial functional component separation. The design consists of an inner core for data storage, and outer core for data protection and a separate read port. This SRAM cell provides a high level of soft error tolerance with a rather low power consumption penalty in comparison with other hardened SRAM designs. The design was optimized for power consumption, write performance, read stability, and soft error tolerance by selectively varying the physical dimensions of the cores. Temperature dependence and impact of voltage scaling were analyzed for the optimized design.