Extending transaction level modeling for embedded software design and validation

In this paper, we propose to extend the Transaction Level Modeling (TLM) approach -initially intended as a higher level abstraction of Register Transfer Level (RTL) hardware (HW) design- to cope with embedded software (SW) design and validation. We aim at introducing new SW TLM concepts which will enable refinement of communication at the SW side. The proposed methodology allows system designers to decide about HW and SW communication architecture jointly, so as to ensure maximum performance efficiency for their designs. As such, multi-processor system-on-chip (MPSoC) heterogeneity would be addressed more efficiently from communication viewpoint.