Keynote address II: Exploiting dynamic hardware reconfigurability for efficiency, performance, and reliability

Summary form only given. Modern FPGA technology allows to modify the hardware configuration of a device not only as a whole, but partially and dynamically at run-time. How to exploit this capability for the implementation of more efficient or less costly systems, for gaining higher system performance or for improvement of life-time reliability issues are topics of current research. In this keynote, we first introduce the reconfiguration capabilities of modern FPGAs and present applications and system implementations that benefit from the on-demand loading of partially reconfigurable hardware modules for so-called multi-mode systems. In the second part of the talk, a method for the on-the-fly composition of pipelined data paths for the acceleration of data base query processing is illustrated as another example of the usefulness of run-time reconfiguration. Finally, a methodology for exploiting partial dynamic hardware reconfiguration for increasing the lifetime of FPGAs is presented. As a matter of fact, physical effects such as NBTI (negative bias temperature instability) and HCI (hot carrier injection) will threaten the correct functionality of FPGA designs in future device generations. In this realm, we present an approach called aging-aware placement for balancing and minimizing the average aging of a given device with the goal to increase the FPGA´s life-time.