The impact of copy-elements on QDI asynchronous FPGA interconnect structure

Asynchronous circuits require some timing constraints met in different timing models. In a well known type of asynchronous circuits named delay insensitive (DI) circuits, there is no timing requirement regarding the delays of different elements. Thus there is no difference between synchronous and DI asynchronous interconnects except when one wants to handle forks. In asynchronous DI systems copy elements are needed to enable us to fork a token to multiple destinations. The size of this copy element is a design parameter in limited design spaces. Particularly to design DI asynchronous FPGAs a limited and configurable copy element is needed. In this paper we explore the impact of copy element size on different metrics in designing an asynchronous FPGA. Our results shows that copy elements of size 2 is best suited for performance and sizes between 2 to 4 is best suited for area saving and copy elements more that 5 are not reasonable.