DocumentCode :
2970022
Title :
Deep-censoring method for early reliability assessment
Author :
Schafft, Harry A. ; Head, Linda ; Lechner, James A. ; Gill, Jason ; Sullivan, Timothy D.
Author_Institution :
Nat. Inst. of Stand. & Technol., Gaithersburg, MD, USA
fYear :
2000
fDate :
2000
Firstpage :
1
Lastpage :
8
Abstract :
Deep censoring is proposed as a direct method to assess the early reliability of semiconductor products. The method characterizes, in particular, the early part of the failure-time distribution and is described in the context of interconnect reliability and electromigration. In this context, it involves stressing a large number of test lines only long enough for some small number of lines to fail, enough to characterize the percentiles of the failure-time distribution that are of interest. Simulations and other calculations show that this approach offers the benefits of much reduced test times and better confidence in sample estimates of early percentiles and of sigma. It can also be used to detect and characterize extrinsic failure-time distributions. An experimental approach is proposed that uses special test structures with many parallel-running test lines. This makes possible early reliability assessments at the wafer level with a full-wafer testing system
Keywords :
electromigration; failure analysis; integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; deep censoring method; early reliability assessment; failure time distribution; interconnect electromigration; semiconductor product; wafer-level testing; Cities and towns; Electromigration; Extrapolation; NIST; Semiconductor device reliability; Stress; System testing; Time measurement; Uncertainty; Yield estimation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Reliability Workshop Final Report, 2000 IEEE International
Conference_Location :
Lake Tahoe, CA
Print_ISBN :
0-7803-6392-2
Type :
conf
DOI :
10.1109/IRWS.2000.911890
Filename :
911890
Link To Document :
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