Reduced pull-in time of PLLS using a triple path PFD and a resistor scalar scheme

A fast pull-in and locking PLL-based frequency synthesizer with a triple-path nonlinear phase frequency detector (TPNPFD) scheme is presented. The proposed scheme can pull the frequency to the target one significantly and can speed-up the lock-in process without losing stability. There are two key features in this novel architecture: the charge-pump current just increases k times of the traditional one while the loop bandwidth increases to komega_C; the loop capacitors are always set to 1/k of the traditional one regardless of the change of the loop bandwidth. Moreover a resistor scalar scheme by using an extra scaling current technique is also presented in this paper for saving chip area of the loop resistor. Thus the chip area and power consumption should be substantially reduced in this proposed scheme.