• DocumentCode
    2970179
  • Title

    Gate reliability comparison of 110 and 100 substrates

  • Author

    Strong, A. ; Wu, E. ; Tews, H. ; Tibel, D. ; Malik, R. ; Cain, O.

  • Author_Institution
    IBM Microelectron., Essex Junction, VT, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    54
  • Lastpage
    56
  • Abstract
    We report, for the first time, intrinsic reliability of SiO2 grown on 100 and 110 substrates. The tunneling current characteristics and barrier height have been analyzed. Three different processes were used to fabricate 6 nm-7 nm gates. In each case, little difference was observed in the gate oxide reliability for the two substrate orientations. The results are explained in terms of the tunneling current and the barrier height
  • Keywords
    electric breakdown; oxidation; reliability; semiconductor-insulator boundaries; silicon compounds; tunnelling; 6 to 7 nm; Si; SiO2; barrier height; gate oxide reliability; oxidation; silicon substrate orientation; time dependent dielectric breakdown; tunneling current; Current measurement; Dielectric substrates; Electric breakdown; Microelectronics; Random access memory; Rivers; Semiconductor device reliability; Thermal stresses; Tunneling; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Reliability Workshop Final Report, 2000 IEEE International
  • Conference_Location
    Lake Tahoe, CA
  • Print_ISBN
    0-7803-6392-2
  • Type

    conf

  • DOI
    10.1109/IRWS.2000.911900
  • Filename
    911900
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2970179