A correlation between highly accelerated Wafer Level and standard Package Level electromigration tests on deep sub-micron via-line structures

So far little trust was put in lifetime projections from highly accelerated Wafer Level electromigration tests on deep sub-micron via-line structures. This was mainly due to a missing correlation between the highly accelerated Wafer Level tests and the conventional Package Level stress technique. We used a constant current stress mode for both, Package Level and Wafer Level, and compared the electromigration test results. The lifetime projection to operating conditions revealed a good correlation between them. Hence our procedure is to be regarded as a promising tool to ensure rapid and cost-effective reliability feedback during technology development