Title :
Layout-aware through-process circuit analysis
Author :
Singh, Rama ; Ziegler, Matt ; Ditlow, Gary ; Heng, Fook-Luen ; Lee, Jin-Fuw ; Lavin, Mark
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights
Abstract :
In the post-90 nm era, due to the advent of low-K1 lithography, variability of circuit parameters, such as effective gate-length and gate-width, is increasing. In this paper, we illustrate how we perform layout aware through process circuit analysis using simulated wafer contours and present results for a full-custom 4:2 compressor circuit.
Keywords :
circuit simulation; lithography; network analysis; semiconductor process modelling; circuit analysis; circuit simulation; low-K1 lithography; semiconductor process modelling; simulated wafer contours; Analytical models; Circuit analysis; Circuit simulation; Circuit testing; Etching; Integrated circuit modeling; Optical design; Semiconductor device modeling; Semiconductor process modeling; Timing; circuit modeling; circuit simulation; lithography; semiconductor process modeling;
Conference_Titel :
Design & Technology of Integrated Systems in Nanoscale Era, 2007. DTIS. International Conference on
Conference_Location :
Rabat
Print_ISBN :
978-1-4244-1277-8
Electronic_ISBN :
978-1-4244-1278-5
DOI :
10.1109/DTIS.2007.4449514
