Title :
Leakage current control of nano-scale full adder cells using input vectors
Author :
Eratne, Savithra ; Nair, Pradeep ; John, Eugene
Author_Institution :
Univ. of Texas at San Antonio, San Antonio
Abstract :
As CMOS technology scaling continues into the nanoscale domain, static or leakage power consumption becomes a vital design parameter. This paper proposes methods for reducing leakage currents by controlling the input vector in nano-scale full adder cells operating in either active mode or standby mode. With proper input vector control, it is possible to obtain over 40% leakage power savings for most of the full adder circuits presented.
Keywords :
CMOS digital integrated circuits; adders; leakage currents; nanoelectronics; CMOS technology scaling; digital CMOS circuit; full adder circuits; input vector control; leakage current control; nanoscale full adder cells; Adders; CMOS technology; Circuits; Control systems; Costs; Delay; Energy consumption; Leakage current; Nanoscale devices; Threshold voltage; full adders; input-vector control; leakage current; nanoscale design;
Conference_Titel :
Design & Technology of Integrated Systems in Nanoscale Era, 2007. DTIS. International Conference on
Conference_Location :
Rabat
Print_ISBN :
978-1-4244-1277-8
Electronic_ISBN :
978-1-4244-1278-5
DOI :
10.1109/DTIS.2007.4449515
