DocumentCode :
2970434
Title :
Electrical equivalent method for thermal stress analysis
Author :
Riemer, Dietrich E.
Author_Institution :
Honeywell Inc., Everett, WA, USA
fYear :
1989
fDate :
22-24 May 1989
Firstpage :
869
Lastpage :
874
Abstract :
A method that can help to improve understanding of thermal-stress problems and is useful for the first-order analysis of thermal stresses in the layered structures of laminates is introduced. The technique models the thermal expansion and the elasticity of each layer as components in a three-terminal equivalent electrical circuit. A model of the laminate is developed by connecting the equivalent circuits of the layers in a network. Currents and voltages are obtained by network analysis. The thermal stresses in the laminate are derived from the branch currents; the local thermal expansion coefficients for the surfaces or for internal bonding interfaces are given by the node voltages
Keywords :
equivalent circuits; laminates; modelling; packaging; printed circuits; stress analysis; thermal expansion; branch currents; elasticity modelling; internal bonding interfaces; laminate model; layered structures; local thermal expansion coefficients; node voltages; packaging; printed circuits; surfaces; thermal expansion modelling; thermal stress analysis; three-terminal equivalent electrical circuit; Elasticity; Equations; Finite element methods; Geometry; Internal stresses; Laminates; Material properties; Thermal expansion; Thermal stresses; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components Conference, 1989. Proceedings., 39th
Conference_Location :
Houston, TX
Type :
conf
DOI :
10.1109/ECC.1989.77847
Filename :
77847
Link To Document :
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