3D memory stacking for fast checkpointing/restore applications

As technology scales, modern massive parallel processing (MPP) systems are facing large system overhead caused by high failure rates. To provide the system-level fault tolerance, the traditional in-disk checkpointing/restart schemes are usually adopted by periodically dumping system states and memory contents to hard disk drives (HDDs). When errors occur, the system can be restored by reading checkpoints from HDDs. The low bandwidth and slow speed of HDDs are now becoming the major bottleneck for the MPP system performance. Consequently, novel checkpointing schemes are need to facilitate the move from Petascale computing to Exascale computing. We have proposed a 3D memory stacking method that leverage the massive number of TSVs between memory layers to help high-bandwidth checkpointing/restore. To validate the proposed scheme, we design a 2-layer TSV-based SRAM/SRAM 3D-stacked chip to mimic the high-bandwidth and fast data transfer from one memory layer to another memory layer, so that the inmemory checkpointing/restartrestore scheme can be enabled for the future exascale computing. The capacity of each SRAM layer is 1Mbit. Each layer contains 64 banks, with each bank contains 256 words and the word length is 64-bit. The final footprint including I/O pad is 2.9 mm × 2 mm. The SRAM dies were taped out in GlobalFoundries using its 130 nm low power process, and the 3D stacking was done by using Tezzaron´s TSV technology. The prototyping chip can perform checkpointing/restart at the speed of 4 K/cycle with 1 Ghz clock.