• DocumentCode
    2970729
  • Title

    Low temperature direct wafer to wafer bonding for 3D integration: Direct bonding, surface preparation, wafer-to-wafer alignment

  • Author

    Gaudin, Gweltaz ; Riou, Gregory ; Landru, Didier ; Tempesta, Catherine ; Radu, Ionut ; Sadaka, Mariam ; Winstel, Kevin ; Kinser, Emily ; Hannon, Robert

  • Author_Institution
    SOITEC, Grenoble, France
  • fYear
    2010
  • fDate
    16-18 Nov. 2010
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In this paper the integration challenges related to oxide-oxide bonding for wafer-to-wafer stacking technology are discussed. Furthermore, interface defectivity, wafer-to-wafer alignment and bond strength data are presented.
  • Keywords
    three-dimensional integrated circuits; wafer bonding; 3D integration; bond strength; direct wafer-wafer bonding; low-temperature bonding; oxide-oxide bonding; surface preparation; wafer-to-wafer alignment; Bonding; Planarization; Plasma temperature; Surface topography; Three dimensional displays; Wafer bonding; 3D stacking; alignment; low temperature direct bonding; wafer to wafer;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    3D Systems Integration Conference (3DIC), 2010 IEEE International
  • Conference_Location
    Munich
  • Print_ISBN
    978-1-4577-0526-7
  • Type

    conf

  • DOI
    10.1109/3DIC.2010.5751472
  • Filename
    5751472
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2970729