Implementation of an Encoder Based on Parallel Structure for LTE Systems

The operation time of the encoder is one of the important implementation issues to meet the timing requirements of LTE systems since the encoder is based on binary operations. In this paper, we propose the design and implementation of an encoder based on parallel structure for LTE systems. Through 8 bits parallel processing of the CRC attachment, code block segmentation, and parallel processor, we could perform the engines for turbo coding and rate matching of each code block in parallel fashion. Experimental results show that although the FPGA slice register, slice LUT, block ram, and clock period of the proposed scheme are 18, 19, 22, and 6% larger than those of the conventional method based on serial processing respectively, our parallel structure reduces the latency about 19 ~ 70% compared with the serial structure. In particular, our approach is more latency efficient in case the encoder processes numerous code blocks.