A Novel Multi-Stack Device Structure and its Analysis for High Power CMOS Switch Design

A novel multi-stack CMOS device structure is proposed, the operation of the structure is fully analyzed for high power CMOS switch design. The structure is also implemented in a standard 0.18-um triple-well CMOS process, and its performance is fully characterized. The proposed switch device incorporates multi-stack NMOS switches, one of which has a switch at the bulk and the others of which have a connection between the bulk and the source in order to provide high power handling capability to the transmit switch side. In order to demonstrate the improvement of power handling capability, performance of the conventional structure and the proposed structure are fully analyzed, compared from various simulation results, and verified with measurement results in detail. Experimental data show that the isolation of the proposed test structure is 25 dB higher at 30 dBm input power level than that of conventional structures, which was caused by the significant reduction of leakage current of the switch device in OFF state. In addition, insertion loss of the Rx switch can be maintained as 1.5 dB by applying body switching technique in 900 MHz.