Efficient coupled noise estimation for RLC on-chip interconnect

This paper presents an accurate, fast and simple closed form solution to estimate crosstalk noise between two adjacent wires in VLSI circuits, using RLC interconnect model. Noise analysis and avoidance techniques are critical steps in deep submicron VLSI technology. Currently noise analysis performed either through circuit or timing simulation. These techniques are still inefficient for analyzing massive amount of interconnect data found in present day integrated circuit. This paper presents an efficient technique for estimation of coupled noise in on-chip VLSI interconnects. This noise estimation metric is an upper bound for RLC circuit, being similar in spirit to Elmore delay in timing analysis. Such an efficient noise metric is required especially for noise and physical design based noise avoidance techniques.