• DocumentCode
    2971975
  • Title

    Design of single neuron on FPGA

  • Author

    Mohamad, Khairudin ; Mahmud, Mohamad Faiz Omar ; Adnan, Fadzilatul Husna ; Abdullah, Wan Fazlida Hanim

  • Author_Institution
    Fak. Kejuruteraan Elektrik, Univ. Teknol. MARA, Shah Alam, Malaysia
  • fYear
    2012
  • fDate
    24-27 June 2012
  • Firstpage
    133
  • Lastpage
    136
  • Abstract
    This paper presents a digital design of neuron architecture on field-programmable gate array (FPGA). The objective of this project is to translate data from electrochemical sensor signals and process the data with neuron structure on digital hardware. The hardware realization of neural network requires investigation of many design issues relating to signal interfacing and design of a single neuron. Analysis focuses on effect of digital design decisions such as module architecture towards data accuracy and delay. The work touches on analogue to digital interfacing, data structure and digital module design that includes adder, multiplier and multiplier accumulator (MAC). A major component of the algorithm is the design of the activation function. The chosen activation function is the hyperbolic tangent which is approximated by Taylor Series expansion. The neuron is evaluated on an Altera DE2-70 FPGA. The performances are evaluated in terms of functionality, usage of resources and timing analysis. For the data structure, it was demonstrated that increasing the fractional bits will increases the precision. The neuron functionality was demonstrated on digital platform. It was found that less delay were produce by using Carry Look Ahead design compared to Ripple Carry Adder by 25% in the MAC performance.
  • Keywords
    adders; carry logic; electrochemical sensors; field programmable gate arrays; logic design; multiplying circuits; neural net architecture; performance evaluation; transfer functions; Altera DE2-70 FPGA; MAC performance; Taylor Series expansion; activation function; analogue to digital interfacing; carry look ahead design; data accuracy; data delay; data structure; digital design decisions; digital hardware; digital module design; digital platform; electrochemical sensor signals; field-programmable gate array; fractional bits; hardware realization; hyperbolic tangent; module architecture; multiplier and multiplier accumulator; neural network; neuron architecture; neuron functionality; neuron structure; performance evaluation; ripple carry adder; signal interfacing; single neuron design; timing analysis; Adders; Arrays; Field programmable gate arrays; Hardware; Neurons; Timing; formatting; insert; style; styling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Humanities, Science and Engineering Research (SHUSER), 2012 IEEE Symposium on
  • Conference_Location
    Kuala Lumpur
  • Print_ISBN
    978-1-4673-1311-7
  • Type

    conf

  • DOI
    10.1109/SHUSER.2012.6268815
  • Filename
    6268815