DocumentCode :
2972053
Title :
The total process cost of selective epitaxial growth (SEG) dielectric isolation process as compared to LOCOS
Author :
Hughes, John C. ; Neudeck, Gerold W.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear :
1997
fDate :
13-15 Oct 1997
Firstpage :
88
Lastpage :
92
Abstract :
The traditional local oxidation of silicon (LOCOS) device isolation process is widely used in the semiconductor industry. Yet, as the need for below 0.18 microns and smaller devices increases, the stress induced leakage currents and device spacing of LOCOS becomes a severe limitation. The use of Shallow Trench Isolation (STI) has also been developed. However, recent improvements in the selective epitaxial growth dielectric isolation (SEG-DI) process have provided an alternative device isolation technique. The simpler SEG-DI process allows for higher packing density and reduced leakage current by eliminating stress. The DI-SEG process has been shown to be approximately the same cost as the LOCOS process
Keywords :
costing; economics; integrated circuit manufacture; isolation technology; leakage currents; vapour phase epitaxial growth; 0.18 micron; LOCOS alternative; device spacing; dielectric isolation process; leakage current reduction; packing density improvement; selective epitaxial growth; stress induced leakage currents; total process cost; Chemical processes; Costs; Dielectric devices; Electronics industry; Epitaxial growth; Leakage current; Oxidation; Semiconductor device modeling; Silicon; Stress;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Manufacturing Technology Symposium, 1997., Twenty-First IEEE/CPMT International
Conference_Location :
Austin, TX
ISSN :
1089-8190
Print_ISBN :
0-7803-3929-0
Type :
conf
DOI :
10.1109/IEMT.1997.626882
Filename :
626882
Link To Document :
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