Title :
Process integration with spin-on-glass sandwich as an intermetal dielectric layer for 1.2 mu m CMOS DLM process
Author :
Yen, Daniel L W ; Rao, Gopal K.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
An intermetal planarization process using a non-etch back spin-on-glass (SOG) sandwich approach has been evaluated in a 1.2- mu m CMOS double-level metal (DLM) process. The process integration issued involved in the selection of a dielectric layer and a planarization process are discussed. In this method of planarization, the SOG is used as a permanent dielectric layer as it is sandwiched between two plasma oxide layers. The physical, planarizing, and electrical properties of the sandwich structure are analyzed. It is demonstrated that this planarization process can be a viable option to other such schemes if the right type of SOG is selected and the coating, baking, and curing processes are optimized to obtain defect-free films.<>
Keywords :
CMOS integrated circuits; VLSI; dielectric thin films; integrated circuit technology; metallisation; 1.2 micron; CMOS double level metal process; baking; coating; curing; electrical properties; intermetal dielectric layer; intermetal planarization process; permanent dielectric layer; plasma oxide layers; process integration; spin-on-glass sandwich; CMOS process; Coatings; Curing; Dielectrics; Etching; Laboratories; Planarization; Plasma applications; Plasma properties; Sandwich structures;
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1988. Proceedings., Fifth International IEEE
Conference_Location :
Santa Clara, CA, USA
DOI :
10.1109/VMIC.1988.14179
