A Viterbi decoder architecture based on parallel processing elements

An architecture for a VLSI Viterbi decoder chip for digital radio systems with trellis-coded modulation based on multiplexing and interleaving of the convolutional code is presented. The architecture is shown to be well suited for a regular and modular chip design by using parallel processing elements. The basic processing element consists of a RAM and a datapath, which call be pipelined to achieve high data rates. The concept of communication between datapath and RAM, which allows the use of standard RAM macros, and the synchronization of the parallel processing elements performed by a simple finite-state machine are discussed. It is shown that by applying pipelining in the datapath, a high data rate can be reached and that with the modularity and regularity of the architecture, no tuning of extremely time-critical paths or time-critical wiring is necessary