A programmable parallel processor architecture for Viterbi detection

The Viterbi signal processor (VSP) is designed to facilitate the programming of the dynamic-programming-like functions that characterize the Viterbi algorithm and other sequential detection methods. The architecture is shown to permit the efficient implementation of sequential decoders for most trellis codes, convolutional codes, and partial-response channels, in software, at rates that are ten to one hundred times faster than those achievable on conventional digital signal processors. Three concurrent and independently programmable subprocessors controlled by a central control unit are described and their programming and architectures characterized. The speed increase occurs because of the special structure and instruction sets of these subprocessors, and the subprocessors (which do not require multiplication) can be implemented with a significantly shorter instruction-execution time than is possible with conventional digital signal processors. It is shown that complex decoders for multidimensional trellis coding can be implemented at sampling rates approaching 1 MHz in software on the VSP