Title :
FPGA implementation of a scalable shared buffer ATM switch
Author :
Shim, J.W. ; Lee, M.K.
Author_Institution :
Dept. of Electron. Eng., Yonsei Univ., Seoul
Abstract :
This paper describes the architecture of a scalable shared buffer ATM switch and FPGA (field programmable gate array) implementation. The proposed ATM switch has a 2-D array of sub-memory blocks as a shared buffer. We can enlarge the buffer capacity by increasing the array size without any change of circuit. The prototype switch has been designed for a 4×4 ATM switch which has a shared buffer for 32 16-byte cells and implemented using FPGA to verify its function. The operating frequency of the designed test-bed is 40 MHz
Keywords :
asynchronous transfer mode; buffer circuits; electronic switching systems; field programmable gate arrays; 16 byte; 2-D array; 40 MHz; FPGA implementation; array size; buffer capacity; field programmable gate array; operating frequency; scalable shared buffer ATM switch; shared buffer; sub-memory block; test-bed; Asynchronous transfer mode; Field programmable gate arrays; Multiplexing; Routing; Signal generators; Switches;
Conference_Titel :
ATM, 1998. ICATM-98., 1998 1st IEEE International Conference on
Conference_Location :
Colmar
Print_ISBN :
0-7803-4982-2
DOI :
10.1109/ICATM.1998.688184
