StarCore: a high-speed ATM switching system

Author

Oba, Nobuyuki ; Suzuki, Ken-ichi ; Kobayashi, Hiroaki ; Nakamura, Tadao

Author_Institution

Res. Lab., IBM Japan Ltd., Tokyo, Japan

fYear

1994

fDate

28 Nov- 2 Dec 1994

Firstpage

139

Abstract

This paper presents a cell scheduling algorithm and its hardware implementation used in an ATM switching system, StarCore. Output contention is resolved by the hardware arbiters in a weighted round-robin fashion, which takes account of the bandwidths allocated to the virtual circuits as well as the priority classes. The arbiter consists of primitive logic gates, which are beneficial for CMOS VLSI implementation, and therefore it gives high-speed arbitration. The circuit simulations indicate that the time for the arbitration of a 64-input switch is 4.2 nsec using 0.7-μm CMOS VLSI technology. The simulations show that StarCore provides lower cell loss probabilities than the conventional round-robin method

Keywords

CMOS digital integrated circuits; VLSI; asynchronous transfer mode; electronic switching systems; integrated circuit technology; logic gates; probability; semiconductor switches; 0.7 micron; 0.7-μm CMOS VLSI technology; StarCore; bandwidth allocation; cell loss probabilities; cell scheduling algorithm; circuit simulations; hardware arbiters; high-speed ATM switching system; high-speed arbitration; output contention resolution; primitive logic gates; priority classes; virtual circuits; weighted round-robin method; Asynchronous transfer mode; Bandwidth; CMOS logic circuits; CMOS technology; Circuit simulation; Hardware; Scheduling algorithm; Switches; Switching systems; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1994. GLOBECOM '94. Communications: The Global Bridge., IEEE

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-1820-X

Type

conf

DOI

10.1109/GLOCOM.1994.513396

Filename

513396