Title :
An analog neural network chip with random weight change learning algorithm
Author :
Hirotsu, Kenichi ; Brooke, Martin A.
Author_Institution :
Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
Although researchers have been engaged in fabrication of neural network hardware, only a few networks implemented with a learning algorithm have been reported. A learning algorithm is required to be implemented on a VLSI chip because off-chip learning with a digital computer consumes too much time to be applied to many practical problems. The main obstacle to implement a learning algorithm is the complexity of the proposed algorithms. Algorithms like backpropagation include complex multiplication, summation and derivatives, which are very difficult to implement with VLSI circuits. The authors propose a new learning algorithm, which is suitable for analog implementation and implement it on a 2.2 mm×2.2 mm neural network chip with 100 weights, using the standard 2.0 μm MOSIS process. The chips have successfully learned the XOR Gate problem.
Keywords :
analogue processing circuits; errors; learning (artificial intelligence); neural chips; 2.0 μm MOSIS process; 2.2 mm×2.2 mm neural network chip; VLSI chip; XOR Gate problem; analog neural network chip; complexity; random weight change learning algorithm; Application software; Circuits; Computer errors; Computer simulation; Equations; Hardware; Machine learning algorithms; Neural networks; Signal processing algorithms; Very large scale integration;
Conference_Titel :
Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on
Print_ISBN :
0-7803-1421-2
DOI :
10.1109/IJCNN.1993.714359