Title :
A low latency kernel recursive least squares processor using FPGA technology
Author :
Yeyong Pang ; Shaojun Wang ; Yu Peng ; Fraser, Nicholas J. ; Leong, Philip H. W.
Author_Institution :
Harbin Inst. of Technol., Harbin, China
Abstract :
The kernel recursive least squares (KRLS) algorithm performs non-linear regression in an online manner, with similar computational requirements to linear techniques. In this paper, an implementation of the KRLS algorithm utilising pipelining and vectorisation for performance; and microcoding for reusability is described. The design can be scaled to allow tradeoffs between capacity, performance and area. Compared with a central processing unit (CPU) and digital signal processor (DSP), the processor improves on execution time, latency and energy consumption by factors of 5, 5 and 12 respectively.
Keywords :
digital arithmetic; field programmable gate arrays; least squares approximations; parallel processing; FPGA technology; kernel recursive least squares algorithm; low latency kernel recursive least squares processor; microcoding technique; nonlinear regression; pipeline processing; vectorisation technique; Field programmable gate arrays; Kernel; Machine learning algorithms; Random access memory; Training; Vector processors; Vectors;
Conference_Titel :
Field-Programmable Technology (FPT), 2013 International Conference on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4799-2199-7
DOI :
10.1109/FPT.2013.6718345
