Title :
A neural network accelerator using matrix memory with broadcast bus
Author :
Arif, Ahmad Fadzil ; Kuno, Shinji ; Iwata, Akira ; Yoshida, Yukio
Author_Institution :
Dept. of Electr. & Comput. Eng., Nagoya Inst. of Technol., Japan
Abstract :
A parallel processing architecture utilizing matrix memory is proposed. Significant improvement of weight updating speed has been achieved for neural network simulations. The proposed system is expandible, fast and within an acceptable performance/cost. Simulating BP on the system is shown and comparisons are made with several other well known systems.
Keywords :
backpropagation; content-addressable storage; neural net architecture; neural nets; parallel architectures; parallel processing; simulation; system buses; backpropagation; broadcast bus; matrix memory; neural network accelerator; parallel processing architecture; simulations; weight updating speed; Broadcasting; Communication switching; Computational modeling; Computer networks; Costs; Hardware; Neural networks; Parallel processing; Real time systems; Switches;
Conference_Titel :
Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on
Print_ISBN :
0-7803-1421-2
DOI :
10.1109/IJCNN.1993.714363
