Analysis and simulation of the buffered-expanded delta fast packet switch

The expanded delta fast packet switch (EDFPS) was proposed for ATM switching. It is constructed by interleaving L delta networks, and it employs a combined external input-output buffering strategy. It was shown that the EDFPS achieves high performance using relatively small values of L. This paper describes an internally-buffered version of the EDFPS. The resulting switch preserves cell-sequencing and employs distributed control concepts. The performance of the switch is evaluated using both analysis and simulation. It is shown that by using internal node buffering, the value of L needed to achieve high performance is significantly reduced. In particular, an L of 4 combined with a single buffer at each switching element inlet results in above 95% maximum throughput for a very large-size switch. Finally, the buffered-EDFPS is examined against nonuniform traffic