The impact of differential “phase” measurement on the characteristics of waiting time jitter

The operation of clock rate adaptation circuits of network synchronizers is based on measuring the “phase” difference between the input and output data streams. In the literature on the analysis of synchronizer performance, it has been assumed that this “phase” difference is a continuous time function. In practice, this is not the case since the data are written and read from a buffer at discrete times. In the paper a model is presented to characterize the synchronizer under discrete time “phase” measurements. Via the simulation of waiting time jitter arising from this model, it can be demonstrated that a discrete time “phase” measurement degrades the performance of jitter reduction techniques that have been proposed in the literature. The performance of a technique which employs a fast clock to overcome this degradation, is discussed in the paper