Title :
High-level test evaluation of asynchronous circuits
Author_Institution :
Dept. of Math. & Comput. Sci., Eindhoven Univ. of Technol.
Abstract :
The present a method for evaluating production fault tests for asynchronous circuits. A novel fault model is defined, based on a high-level circuit description, allowing the evaluation of production tests on the design level. This evaluation method is used in the test generation for an asynchronous 22 k transistor DCC error corrector IC, resulting in a fault coverage of 99.8%
Keywords :
VLSI; asynchronous circuits; error detection codes; logic testing; asynchronous 22 k transistor DCC error corrector IC; asynchronous circuits; fault model; high-level circuit description; high-level test evaluation; production fault tests; Asynchronous circuits; Circuit faults; Circuit testing; Costs; Design for testability; Detectors; Energy consumption; Integrated circuit testing; Production; Very large scale integration;
Conference_Titel :
Asynchronous Design Methodologies, 1995. Proceedings., Second Working Conference on
Conference_Location :
London
Print_ISBN :
0-8186-7098-3
DOI :
10.1109/WCADM.1995.514643
