A hardware acceleration of a phylogenetic tree reconstruction with maximum parsimony algorithm using FPGA

In this paper, we present a hardware acceleration approach for a phylogenetic tree reconstruction with maximum parsimony algorithm using FPGA. The algorithm is based on a stochastic local search with the progressive tree neighborhood. The hardware architecture is divided in different units, each of which performs a specific task of the algorithm, to take advantage of the parallel processing capabilities of the FPGA. We show results for four real-world biological datasets, and compare them against results from two programs: our C++ implementation and TNT (a program for phylogenetic analysis). High acceleration rates are obtained against our C++ implementation, but not against TNT, which even shows to be faster in some cases. We conclude our work with a discussion on this issue.