Implementation of a bandwidth optimized wideband-integrator on FPGA

Author

Sinha, V.K. ; Singh, Ashutosh ; Khadeer, M.A. ; Sandeep, Vuddanti

Author_Institution

Dept. of Electron. & Commun., IIIT Allahabad, Allahabad, India

fYear

2012

fDate

21-22 Nov. 2012

Firstpage

1

Lastpage

5

Abstract

Analysis of digital design and implementation of Nam Quoc Ngo´s 32 bit integrator is being presented in this paper. The design objective is to realize a wider bandwidth integrator. Proposed design is optimized using conditional sum adder for addition, Radix 4 Booth with Wallace tree carry save adder algorithm for multiplication and a modified algorithm to calculate 2s complement of a binary number. The time complexity of proposed design is compared with hardware design generated by Matlab Xilinx system generator and design by default hardware of DSP48 slices on virtex-5. Proposed design is having larger bandwidth compared to the design by system generator and DSP48 slice based design.

Keywords

adders; field programmable gate arrays; integrating circuits; logic design; DSP48 slice; FPGA; Matlab Xilinx system generator; Radix 4 Booth; Wallace tree; bandwidth optimized wideband integrator; binary number; carry save adder algorithm; conditional sum adder; digital design; twos complement; Adders; Delay; Field programmable gate arrays; Finite impulse response filter; Interpolation; Wideband; Digital Integrator; FPGA; IIR filter; wideband and conditional sum adder;

fLanguage

English

Publisher

ieee

Conference_Titel

Computing and Communication Systems (NCCCS), 2012 National Conference on

Conference_Location

Durgapur

Print_ISBN

978-1-4673-1952-2

Type

conf

DOI

10.1109/NCCCS.2012.6412984

Filename

6412984