An FPGA-cluster-accelerated match engine for content-based image retrieval

Author

Chen Liang ; Chenlu Wu ; Xuegong Zhou ; Wei Cao ; Shengye Wang ; Lingli Wang

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2013

fDate

9-11 Dec. 2013

Firstpage

422

Lastpage

425

Abstract

In this paper, a high-performance match engine for content-based image retrieval is proposed. Highly customized floating-point(FP) units are designed, to provide the dynamic range and precision of standard FP units, but with considerably less area than standard FP units. Match calculation arrays with various architectures and scales are designed and evaluated. An CBIR system is built on a 12-FPGA cluster. Inter-FPGA connections are based on standard 10-Gigabyte Ethernet. The whole FPGA cluster can compare a query image against 150 million library images within 10 seconds, basing on detailed local features. Compared with the Intel Xeon 5650 server based solution, our implementation is 11.35 times faster and 34.81 times more power efficient.

Keywords

content-based retrieval; field programmable gate arrays; floating point arithmetic; image matching; image retrieval; local area networks; parallel processing; power aware computing; CBIR system; FPGA cluster; FPGA-cluster-accelerated match engine; content-based image retrieval; dynamic range; floating-point units; high-performance match engine; interFPGA connections; library image; local features; match calculation arrays; power efficiency; standard Ethernet; standard FP units; Delays; Field programmable gate arrays; Image retrieval; Libraries; Media; Servers; CBIR; FPGA cluster; high performance computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology (FPT), 2013 International Conference on

Conference_Location

Kyoto

Print_ISBN

978-1-4799-2199-7

Type

conf

DOI

10.1109/FPT.2013.6718404

Filename

6718404